Tried to get blitter on 16Mhz clock from MMU pin 5 but it did get messy, division of clock counts in fpga code did not seem to improve anything. I wish I had designed some pads around clock source configuration but yeah... Thanks to great input from @Icky and a lot of hacking hours not fully underst...

More I look at the timings, more I think PLL should be clocked from external crystal and CLK as signal synced to Atari. This would sync bus events but not impede logic operations. Perhaps that's a dead ally but first impression is that processing is consuming too many cycles. Or fiddle with P_CYCLE_...

Thanks for the tip re. resolution. I don't have working original blitter to make such comparison so can only compare to other sets of test data. Will rerun with med res though. Re. where I am, no surprise at the same starting point. Timing is off but that's the next step. First was to get it going a...

And here we are. 4 layer boards turned out okay from Aisler but only 2 out of 3 passed the testing at the factory... wondering will I ever get my 3rd board :roll: pcb.jpg Assembled and fitted this to my Atari Mega ST 1. Almost stock, 8Mhz , 4M upgrade and TOS 2.06 hack. assem.jpg Thankfully no board...

Kind of short on real estate due Cyclone IV being a large chip with tons of needed voltages plus external flash but this is what I have. Creation of blitter library with Atari PLCC socket... lovely part due HD copies of schematics and no doubts on pinout ;) This is still prior optimization but was u...

I see, so PLL is clocked by either 8 or 16MHz from ST as external clock without an oscillator. Interesting as there's one on Suska stand-alone IC board. GTL is open drain so no extra diodes or logic required for DTACK etc, 200k for pull-up of D/Gref. If there would be ready product to buy I would sp...

As starting point I took Suske BLT101643 (WF101643IP_TOP), compiled no problem with Quartus 18.0. Noticed there are two versions, one which seems to be stand-alone IC and the other one probably integrated with other ICs in the same FPGA chip judging by additional signals and pins.

98% or 99% is much better than no blitter so I will experiment with this project as well. Interestingly it fits my Cyclone IV which is not the smallest package but doable by hand while Mega has got some room under the hood. For bidirectional bus'es 3xGTL2000 will do the job with 66 lines available. ...

That is a wow , recognized GLT voltage level shifters as gateway to old 5V world. Will definitely read through as have some Max IIs and Cyclone IVs around from another project.

C302183-002 STE integrated glue + blitter are much more accessible. I guess if that would be a matter of a simple PCB adapter it would have been done a long time ago to port this to older ST machines? Hope is strong.