TF CD32 Riser Revision 2 Design Complete

TF CD32 Riser

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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire »

arkadiusz.makarenko wrote: Sat Jan 02, 2021 3:33 pm Ufff. I started nervously biting my nails :D
There is an issue.

Something between the TF accelerators and the riser is resulting in the reset line being held low. every now and again it pops out of that mode but i can for sure see the reset lines held low..

Is reset from the riser floating when not set?

EDIT: also sysinfo with the TF360 reports 21 instead of 70.. so defo some performance left of the table.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko »

terriblefire wrote: Sat Jan 02, 2021 3:54 pm
arkadiusz.makarenko wrote: Sat Jan 02, 2021 3:33 pm Ufff. I started nervously biting my nails :D
There is an issue.

Something between the TF accelerators and the riser is resulting in the reset line being held low. every now and again it pops out of that mode but i can for sure see the reset lines held low..

Is reset from the riser floating when not set?
I have KBD_Clock set up for Open Drain, and I pull it low when required.
But On STM32 startup I have moment when keyboard do the reset?
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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire »

arkadiusz.makarenko wrote: Sat Jan 02, 2021 4:09 pm
terriblefire wrote: Sat Jan 02, 2021 3:54 pm

There is an issue.

Something between the TF accelerators and the riser is resulting in the reset line being held low. every now and again it pops out of that mode but i can for sure see the reset lines held low..

Is reset from the riser floating when not set?
I have KBD_Clock set up for Open Drain, and I pull it low when required.
But On STM32 startup I have moment when keyboard do the reset?
yeah for some reason its not coming out of that. I had an older version of the firmware i hacked that ran the keyboard reset to the motherboard right at the moment the arm boots. and that worked really well.

CD32 reset setup is the worst of any amiga btw.
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indicates how much hurting you shall receive."
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko »

terriblefire wrote: Sat Jan 02, 2021 4:12 pm
arkadiusz.makarenko wrote: Sat Jan 02, 2021 4:09 pm

I have KBD_Clock set up for Open Drain, and I pull it low when required.
But On STM32 startup I have moment when keyboard do the reset?
yeah for some reason its not coming out of that. I had an older version of the firmware i hacked that ran the keyboard reset to the motherboard right at the moment the arm boots. and that worked really well.

CD32 reset setup is the worst of any amiga btw.
I have deeply modified keyboard routine to avoid long blocking delays. Maybe I am sloppy somewhere with setting modes or there are empty sends triggeredby timer.

With performance, there is still some room for improvement I guess, but I don't think it will match 1:1.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire »

I think for the keyboard you can block all day because its clocked. It doesnt matter if the CPLD interrupts.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko »

terriblefire wrote: Sat Jan 02, 2021 4:44 pm I think for the keyboard you can block all day because its clocked. It doesnt matter if the CPLD interrupts.
my main loop routine manages registeres and usb hid report decode etc. Plus If I ever look at FlashFloppy or soundcard like 10ms (?) waits between each key send seemed as waste of resources.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire »

arkadiusz.makarenko wrote: Sat Jan 02, 2021 4:51 pm
terriblefire wrote: Sat Jan 02, 2021 4:44 pm I think for the keyboard you can block all day because its clocked. It doesnt matter if the CPLD interrupts.
my main loop routine manages registeres and usb hid report decode etc. Plus If I ever look at FlashFloppy or soundcard like 10ms (?) waits between each key send seemed as waste of resources.
Ah fair enough. I need to dig into what is holding the reset line low.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko »

terriblefire wrote: Sat Jan 02, 2021 4:55 pm
arkadiusz.makarenko wrote: Sat Jan 02, 2021 4:51 pm

my main loop routine manages registeres and usb hid report decode etc. Plus If I ever look at FlashFloppy or soundcard like 10ms (?) waits between each key send seemed as waste of resources.
Ah fair enough. I need to dig into what is holding the reset line low.

KBD_Clock is on Port B the same as Data lines, so maybe mode is being changed for this pin during bus data write?
I will have a look at this hopefully tonight.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire »

Just FYI..

here is the times you're getting
bfe001.JPG
bfe001.JPG (59.19 KiB) Viewed 3420 times
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko »

Could you check this? @terriblefire
There are two changes, KBD_Clock is fixed to one setting Open Drain and never reconfigured. I checked on datawrites and seems to be ok.
second change is simple optimization -OFast insead of -ODebug maybe speed will be a little but better?
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