Tried multiple things , not having much luck. It's "stabbing in the dark" type diagnostics
I just tried EMUTOS but did not make any difference with the experimental firmware.
Tried multiple things , not having much luck. It's "stabbing in the dark" type diagnostics
Sorry to insist with this, but have you performed timing analysis?
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wire SLOW = (~altram_access_int ) ;
No.
EmuTOS might help your stock firmware test (because of my FRB driver mistake), but I doubt it will make any difference to your homebrew firmware if the timing has been taken out of whack.
I've tried just about every combination of everything already. Nothing really makes any odds. I just use my hacked firmware as it didn't have floppy issues.
If there are timing issues, as you both suspect, then results might always be unpredictable and very difficult to diagnose. You have to constrain the design properly and perform a full timing analysis. Otherwise you are IMHO shooting in the dark.
Just to go back to this as I didn't have time yesterday.
That sounds a very reasonable approach indeed. I'm not an expert on this Xilinx’s CPLD family, but I'll try a timing analysis later.
No idea if this the case here, but it might be very well a timing problem. When you test it and it works, it just mean it works on your own setup on specific conditions. But conditions might be different for others. This includes of course differences in voltage and temperature. But also each chip has a different performance. Let alone if somebody decides to use a compatible SDRAM chip from a different manufacturer.So my approach has been to reduce complexity as much as possible, set everything to speed mode and measure the results. If it appears to work, test it extensively. If it doesn't, attempt mitigation and go again.
What I hadn't quite understood from Exxos' posts (he works on it during the day, I try to follow it and act on it in a couple of hours at night -- we sometimes get out of sync) was that the stock firmware was not working reliably for him.
Off the top of my head between ST and STE, not sure if it affects your case, but are you aware about the different DTACK behavior when accessing the PSG? I remember this affected an Exxos accelerator, but I think it was a much faster one?It's possible (more than likely now I see issues with stock too) that there are differences between the H5 and STE that need to be accommodated too.