DSTB1 exxos first tests & experimental firmware.

Discussion and support for the DSTB1 & DFB1 boosters by BadWolf..
ijor
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Re: DSTB1 exxos first tests & experimental firmware.

Post by ijor »

Badwolf wrote: Tue May 10, 2022 4:56 pm
ijor wrote: Tue May 10, 2022 4:44 pm That's all it takes (for a basic clock TIMESPEC constrain).
That I can do (and have done previously). Is that useful by itself?
It is. Among other things it will warn you if some signal on the state machine is not meeting timing. As long as it doesn't, and assuming everything else is correct, it means you are not using too many terms. Of course, you must check the warnings, otherwise you would defeat the whole purpose of this.

Note that this applies only to the internal synchronous logic. This constrain doesn't check the external interface or the asynchronous aspects.

Also it seems the timing analyzer has a bug and can't detect the clock inversion automatically unless you are using a global clock. In this case it doesn't detect the "nexstate" - "state" transfers works on opposite edges.

Even by itself, a simple clock constrain would also help the compiler to optimize the design with a timing-driven compilation. This is much more important on an FPGA design though.
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Badwolf
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Re: DSTB1 exxos first tests & experimental firmware.

Post by Badwolf »

ijor wrote: Tue May 10, 2022 9:20 pm
Badwolf wrote: Tue May 10, 2022 4:56 pm That I can do (and have done previously). Is that useful by itself?
It is. Among other things it will warn you if some signal on the state machine is not meeting timing. As long as it doesn't, and assuming everything else is correct, it means you are not using too many terms. Of course, you must check the warnings, otherwise you would defeat the whole purpose of this.

Note that this applies only to the internal synchronous logic. This constrain doesn't check the external interface or the asynchronous aspects.
Actually, that's the part I understood how to test the least, so thank you for that. I'd missed the internal registers referenced.

I've starting redevelopment of the SDRAM driver based on your feedback so thanks very much for all of this so far.

What doesn't help, mind, is I've got two copies of ISE. Both purportedly the same version number, both produce identical JED files (bar the 'produced on' line at the top) yet one passes my timing specs and the other doesn't!

Bloody ISE... :?

BW
DFB1 Open source 50MHz 030 and TT-RAM accelerator for the Falcon
DSTB1 Open source 16Mhz 68k and AltRAM accelerator for the ST
Smalliermouse ST-optimised USB mouse adapter based on SmallyMouse2
FrontBench The Frontier: Elite 2 intro as a benchmark
ijor
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Re: DSTB1 exxos first tests & experimental firmware.

Post by ijor »

Badwolf wrote: Tue May 10, 2022 10:07 pm What doesn't help, mind, is I've got two copies of ISE. Both purportedly the same version number, both produce identical JED files (bar the 'produced on' line at the top) yet one passes my timing specs and the other doesn't! Bloody ISE... :?
I've found that the latest version of ISE is quite buggy with XC9500XL projects. Seems you need to reset the project, at least, whenever you make changes to the timing constraints: "Clean Project Files ..." at the Projects menu. It is possible that older versions actually work better.

You can also run the timing analyzer separately. This gives you more detailed options for the analysis and report.
http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
http://pasti.fxatari.com
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Badwolf
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Re: DSTB1 exxos first tests & experimental firmware.

Post by Badwolf »

@ijor,

A couple of nights ago I started a refactor of my SDRAM controller based on your feedback. So far things seem to have gone well and it's now behaving itself at both 16 and 8MHz. Primarily I think this was down to your suggestion to avoid asynchonous lines in the state machine logic.

I still need to accomodate the RMW logic (Exxos has tested that this is failing on my current logic) which is another bug you identified.

Basically, thank you for the help. I'll be putting up the modifications to date a little later this evening.

Cheers,

BW.
DFB1 Open source 50MHz 030 and TT-RAM accelerator for the Falcon
DSTB1 Open source 16Mhz 68k and AltRAM accelerator for the ST
Smalliermouse ST-optimised USB mouse adapter based on SmallyMouse2
FrontBench The Frontier: Elite 2 intro as a benchmark
ijor
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Re: DSTB1 exxos first tests & experimental firmware.

Post by ijor »

Badwolf wrote: Fri May 13, 2022 5:20 pm @ijor,

A couple of nights ago I started a refactor of my SDRAM controller based on your feedback. So far things seem to have gone well and it's now behaving itself at both 16 and 8MHz.
Glad it is working fine. One thing I forgot, if you implement all the changes, including rewiring RAMCLK, the clock skew would be changed significantly. You might need to check if it's better to work with an inverted clock or not (posedge or negedge).

I think that at that point it would be possible to perform an accurate timing analysis of the external interface. But it might be worth to scope the skew anyway (see the relation between the clock and any control signal at the SDRAM chip).
http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
http://pasti.fxatari.com
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Badwolf
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Re: DSTB1 exxos first tests & experimental firmware.

Post by Badwolf »

ijor wrote: Fri May 13, 2022 5:51 pm One thing I forgot, if you implement all the changes, including rewiring RAMCLK, the clock skew would be changed significantly. You might need to check if it's better to work with an inverted clock or not (posedge or negedge).
Yes you did say that, ta.

Here's the work in progress so far. I've not fixed the RMW bug yet. I couldn't fit the counter stuff into the other always block either, but greatly simplified.

https://github.com/dh219/DSTB/blob/dev_ ... au_sdram.v

I need to examine the end of cycle latches next.

BW
DFB1 Open source 50MHz 030 and TT-RAM accelerator for the Falcon
DSTB1 Open source 16Mhz 68k and AltRAM accelerator for the ST
Smalliermouse ST-optimised USB mouse adapter based on SmallyMouse2
FrontBench The Frontier: Elite 2 intro as a benchmark
ijor
Posts: 428
Joined: Fri Nov 30, 2018 8:45 pm

Re: DSTB1 exxos first tests & experimental firmware.

Post by ijor »

Badwolf wrote: Fri May 13, 2022 7:40 pm Yes you did say that, ta.
Oh, sorry. So I actually forgot that I didn't :oops: I think I am starting to speak too much out of excitement for the subject. Sorry
http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
http://pasti.fxatari.com
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