Sometimes one things leads to another.
Christian dropped me a note to tell me a story from his past about signal integrity. This got me thinking about how few control lines are actually involved when I speak to the DSP. Really it's only AS, UDS, LDS (outbound), XDTACK and XCPUCLK (inbound).
Previous experience suggested the clock, and DTACK were fine, but I'd observed fiddling a bit of capacitance here and there on AS had caused things to go in and out of working.
So I started re-routeing some pins on the CPLD so I could add some inline termination to AS, UDS, LDS. I did AS first and... it worked.
It worked really well. Really stably. Even accelerated.
So I tried different termination settings. It all still worked. Even a straight wire worked. So it must be timing again... It occurred to me that by driving AS from the other side of the CPLD, there was an inherent delay from what I had before -- but I didn't see how that could affect things.
My UDS and LDS wires, however. They take their cue from the XAS line. But that was now an input! So OK, it's a delay on the UDS and LDS lines relative to the AS line that helps things.
But I experimented with this before. A (practically) zero delay didn't help. 10ns made things almost work. 20ns -- too much. But this was done with trying to trigger on a faster clock edge and it wasn't really reliable. I couldn't really see how UDS asserting a few nano seconds here or there would affect the GALS, which is to whom I speak, though.
Then it hit me. It's not the assertion (falling) edge. It's the
rising edge! All my experiments with flip flops had varied the falling edge, but the rising edge was always shut off by AS going high. But
delaying the deassertion of UDS and LDS must be the answer!
I thought back to when the DSP samples the data. At the
rising edge of DSP_CS. That edge is driven almost entirely by AS. But UDS and LDS drive the A0 line! If AS deasserts, takes UDS and LDS with it. A0 will be undefined as DSP_CS goes high some nanoseconds later!
Aaarrgh! What a fool I've been all this weeks!
So I rigged up a quick flip flop that did my delay experiment in reverse. Assert UDS/LDS simultaneously, but only deassert LDS and UDS the clock edge
after AS deasserts.
- as_x_uds_full.png (10.04 KiB) Viewed 2232 times
BadMood has now been running for an hour in 50MHz accelerated mode.
Thanks to Exxos, Christian and everyone else who's chipped in with ideas on this. I think (and
hope) this is finally it and I can move on to the FPU.
I am an absolute idiot.
BW