exxos's Atari, Amiga & retro forum

Fantastic! Are you planning to engineer the firmware from scratch or start with one of the existing (non cycle accurate) implementations, like minimig?

Awesome idea and the board looks sweet.

Will you be releasing the Verilog/VHDL rtl source?

Beyond a physical board, cycle-accurate replacement modules will help a variety of causes like other FPGA-based amiga reimplementations.

Thanks for your efforts!

I'm planning to do a re-implementation but of course i'll just start with a compile of Minimig to get going.. or maybe aoOCS. I think that code is cleaner anyways.

After i have a baseline to prove it works i'll get traces on the Logic analyser and watch the cycles with real agnus vs re-agnus.

I'll release it all but with the usual 6 month delay to keep the parasites from making a quick buck.

Here's what I use for capturing Agnus traces on my HP 16700s and 16900:

https://www.techtravels.org/2013/03/bug ... -on-agnus/

Amazing, Amiga will never die as long as people keep doing great projects like this.

(Chucky's 1.5 ReAmiga release got me started on a new machine also)

Maximilian wrote: ↑Tue May 26, 2020 4:41 pm Thaty is an amazing project,
(wasn't someone else doing the same?)

@Icky has a similar board for the H4 but based on MAX 10 chips.

Are there any pins over on the FPGA and the bus buffers?
If wired to a couple of pads those could be used for upgrades or feature selection like Pal/Ntsc.
Just a thought..

Yeah i am toying with ideas for stuff like that but TBH right now the goal is just to compile minimig into it.

a500king wrote: ↑Tue May 26, 2020 8:39 pm Here's what I use for capturing Agnus traces on my HP 16700s and 16900:

https://www.techtravels.org/2013/03/bug ... -on-agnus/

bug_katcher_installed.jpg

i'd thought about this then realized almost all of those pins come out to the either the 68000 socket or the ram expansion socket.

5 pieces are ordered with partial assembly. Without buffers or fpga they were £7 each.

Remaining BOM is 1 x ICE40 FPGA. 10 x bus buffers. 10 x 100nF 0805 Caps

Maximilian wrote: ↑Tue May 26, 2020 4:41 pm Thaty is an amazing project,
(wasn't someone else doing the same?)

Found it (German):
https://www.forum64.de/index.php?thread ... /&pageNo=1
Not a lot of info on it, he digitized high res die pictures and used his software to reproduce a schema.

He is using a MAX10 chip also, but he's very busy so his project will probably te some time to complete....

Maximilian wrote: ↑Wed May 27, 2020 2:09 am Found it (German):
https://www.forum64.de/index.php?thread ... /&pageNo=1
Not a lot of info on it, he digitized high res die pictures and used his software to reproduce a schema.

He is using a MAX10 chip also, but he's very busy so his project will probably te some time to complete....

Ok cool. I have the schematics in pdf form and a few other sources.

But the first thing to do for me is get the whole thing running roughly with Minimig/aoOCS etc. Just to prove the hardware works.