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SDRAM timings
Posted: Mon May 24, 2021 9:16 am
by terriblefire
I've read some nasty comments about my SDRAM controller... so i figured i'd post my timing diagram and let people tell me where i can improve it..
- sdram.png (35.54 KiB) Viewed 3686 times
The ram we have requires 20ns between RAS and CAS (ACT and RD here). So its got to be at least 2 clocks at 100Mhz. And the CAS latency (the time between CAS and data arriving on the bus) is 2 ram clock cycles. We have burst but lets just look at random access for now.
I'm using wavedrom for the diagrams..
Code: Select all
{signal: [
{name: 'CPU', wave: '345.....63|',data: ['S0', 'S1', 'S2', 'S3', 'S0']},
{name: 'CLKRAM', wave: 'p..................'},
{name: 'CLKCPU', wave: '1010101010101010101'},
{name: 'AS30', wave: '10........1|'},
{name: 'DS30', wave: '10........1|'},
{},
{name: 'CMD', wave: '.x3xx45xxxxxxxxxxxx',data: ['ACT', 'RD','RDP']},
{name: 'D', wave: 'x.......3.x...', data: ['data']},
{},
{name: 'STERM', wave: '1.......0.1|'}
]}
If people are so scathing about my ram controller then please tell me how it can be improved.
Re: SDRAM timings
Posted: Mon May 24, 2021 11:05 am
by dalek
The only board I know of that you open-sourced an sdram controller is the TF330 right?
I guess the haters are too busy to submit a patch.
Re: SDRAM timings
Posted: Mon May 24, 2021 11:34 am
by terriblefire
dalek wrote: ↑Mon May 24, 2021 11:05 am
The only board I know of that you open-sourced an sdram controller is the TF330 right?
I guess the haters are too busy to submit a patch.
Yeah TF330 ... Its the same SDRAM controller as in the MiST(er) archie core. Same in all the TF boards.
Re: SDRAM timings
Posted: Thu Jun 03, 2021 2:43 pm
by terriblefire
Similarly for the 060 timings...
- wavedrom.png (16.65 KiB) Viewed 3392 times
Code: Select all
{signal: [
{name: 'CPU', wave: '345.....63|',data: ['S0', 'S1', 'S2', 'S3', 'S0']},
{name: 'CLKRAM', wave: 'p..................'},
{name: 'CLKCPU', wave: '1010101010101010101'},
{name: 'AS30', wave: '10........1|'},
{name: 'DS30', wave: '10........1|'},
{},
{name: 'CMD', wave: '.x3xx45xxxxxxxxxxxx',data: ['ACT', 'RD','RDP']},
{name: 'D', wave: 'x.......3.x...', data: ['data']},
{},
{name: 'STERM', wave: '1.......0.1|'}
]}
Re: SDRAM timings
Posted: Fri Jun 04, 2021 7:29 pm
by Badwolf
terriblefire wrote: ↑Mon May 24, 2021 9:16 am
I've read some nasty comments about my SDRAM controller... so i figured i'd post my timing diagram and let people tell me where i can improve it..
Crikey, tough crowd. If they don't like yours, they'll hate mine!
Yours (536) and mine (DFB1) average to almost the same benchmarks using different clock strategies, so I think it's close to the limit (I should say that mine has segments of yours in it to the point I've made sure it inherits your licence and has your name in it against the logic assemblies I've copied but otherwise it's derived from the ground up).
Only things I could genuinely think to ask are if transitions are really on rising edge as shown in your diagram (wouldn't falling edge make more sense?) and is there any unnecessary STERM delay on writes (no CAS latency)?
BW
Re: SDRAM timings
Posted: Fri Jun 04, 2021 8:24 pm
by terriblefire
Badwolf wrote: ↑Fri Jun 04, 2021 7:29 pm
Only things I could genuinely think to ask are if transitions are really on rising edge as shown in your diagram (wouldn't falling edge make more sense?) and is there any unnecessary STERM delay on writes (no CAS latency)?
I'm a rising edge kinda guy
Its rising edge + settling time... which can be 10ns on these CPLDS.
Re: SDRAM timings
Posted: Fri Jun 04, 2021 9:47 pm
by Badwolf
terriblefire wrote: ↑Fri Jun 04, 2021 8:24 pm
Its rising edge + settling time... which can be 10ns on these CPLDS.
Ah yeah, fair enough. Your clock is #jollyfast after all.
I think I've come to the end of the road with this iteration of my firmware -- it's not a happy bunny fitting into even a 288 -- so I was thinking of actually trying to port your whole 330 source to my card. Gayle and Autconfig stuff out, DSP, auto vector emulation etc in. Might cancel out.
Anyway point being it'd then give a nice before-and-after memory speed comparison. I'll shout if it works and if there's any significant difference one way or the other.
BW
Re: SDRAM timings
Posted: Sat Jun 05, 2021 12:00 am
by terriblefire
Thanks...
Given how much work is involved in these cards and given i have started from a blank sheet on about 10 different boards im not at all upset if someone spots a mistake etc.
What gets/got me was that people said that the things wouldnt work before i even built most of them. I'm sure i could spend 5 years and tune the Tf1260 to perfection but.. it works now.. so why not let people use it.