Currently, I have an almost complete TF530r3, I'm waiting for the SRAMs to arrive, but all other components are already soldered, and CPLDs are programmed. Diagrom is also on the way. So, I have some questions at this point:
- Is it possible to do a boot test, without fastram, just to see if the 68030/Bus CPLD are working? I have read about wiping the RAM CPLD on the r2 version, but I didn't find any info on the procedure for r3 boards. Should I wipe the CPLD? Or desolder it? Do I need a specific CPLD code version? Should I modify it somehow and recompile? (I don't have the sources, by the way)
- Is there any installation guide around, for the r3 version? Does it need any external wire, like the r2 needed?
- Is there a way to simulate the FPU load, and avoid damping on the clock signal? May the absence of SRAMs cause damping of any other signals?
- I soldered a 25MHz crystal, but I also have 40 and 50 available. My intention is to test and debug at 25, then go for 40 or 50 and see if it runs stable. Are there specific firmwares for 25, 40 and 50? Is there a firmware that will work on all speeds?
- Is the latest firmware (tf53x_2019_02_18_alpha.zip) really the best, both for TF530 and TF534? Is there any feature/advantage on previous FWs that might be useful?