MC68060 TT Behaviour

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MC68060 TT Behaviour

Post by terriblefire »

I'm working on the new firmware and i've dicovered what I think is a bit of odd behaviour with the 68060 CPU. Maybe its just happening on some 68060 CPUs but i cant find it in the manual. Once again this is an example of Manuals and reality being out of sync.

I'm looking at the timing of the TT signals on the 68060. For those unfamiliar this is the Transfer Type register. It controls whether the cycle is a burst (Move16), Normal (memory access) or interrupt acknowledge (or breakpoint ack etc). e.g.

Table 2-2. Transfer-Type Encoding

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If run the 68060 bus at full speed with CLKEN = 0 everything works ok. At about 90Mhz this becomes a bit much for the CPLDs so i want to half this again when talking to the Amiga so i alternate CLKEN.

The trouble is that this causes TT to be 1 cycle delayed in being correct.

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Which causes the bus translator to do an interrupt acknowledge cycle instead of fetching the first word from RAM. This is massively infuriating and does not matchup with what the manual says...

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tt_timing.JPG
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And yes i have tried this with 90 degree 180 degree and 0 degree CLKEN timing. No difference. This is why I dont really accept it when people say just read the manual. The manuals are often very wrong.

I'm thinking it might not be possible to use CLKEN this way to slow down the bus cycles and give the bus cpld a break.
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Re: MC68060 TT Behaviour

Post by stephen_usher »

When I saw the title I thought you'd somehow got the 68060 running on an Atari TT! :-)

Manual inaccuracy is a right pain. Often the manuals are written to the original specification and not how the actual silicon works.
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Re: MC68060 TT Behaviour

Post by exxos »

terriblefire wrote: Thu Dec 02, 2021 9:08 am And yes i have tried this with 90 degree 180 degree and 0 degree CLKEN timing. No difference. This is why I dont really accept it when people say just read the manual. The manuals are often very wrong.

I'm thinking it might not be possible to use CLKEN this way to slow down the bus cycles and give the bus cpld a break.
My first thought was it seems it can't change speeds without clock switching ? But it doesn't say much in the data sheet..
The CLKEN input is used on the MC68060 to enable to the clock edges on which the bus controller will
respond. By toggling the CLKEN pin, it is possible to operate the MC68060 on an external bus at 1/2 or 1/4
the speed of the processor clock.
Clock edges of what clock ?! It doesn't seem to make sense, why would toggling a pin make the bus slower ?! Almost sounds like a pulse skipping type of thing. Like when a rising edge is about to happen, switch the EN so its looking for the falling edge, so it would ignore the rising edge.. Then when it gets near the falling edge, switch EN again so it looks for the rising edge.. But that would be bonkers, and on that basis you could slow the bus down as much as you want.
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Re: MC68060 TT Behaviour

Post by derkom »

stephen_usher wrote: Thu Dec 02, 2021 10:03 am When I saw the title I thought you'd somehow got the 68060 running on an Atari TT! :-)
If anyone could make that happen, it'd be @terriblefire. ;)
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Re: MC68060 TT Behaviour

Post by terriblefire »

exxos wrote: Thu Dec 02, 2021 10:16 am Clock edges of what clock ?! It doesn't seem to make sense, why would toggling a pin make the bus slower ?! Almost sounds like a pulse skipping type of thing. Like when a rising edge is about to happen, switch the EN so its looking for the falling edge, so it would ignore the rising edge.. Then when it gets near the falling edge, switch EN again so it looks for the rising edge.. But that would be bonkers, and on that basis you could slow the bus down as much as you want.
Its a clock enable line. It means things have double the setup time. Every other clock is ignored externally but internally the CPU can chug away on things. I'm not seeing why this doesnt make sense?

This also means external signals like TS/TA are asserted for 2 clocks externally instead of 1 clock but should only be sampled when the clock enable line is asserted. The effect is to half the bus speed for things that need >15ns setup time.

Screenshot 2021-12-02 at 10.55.33.png
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Screenshot 2021-12-02 at 10.56.21.png
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Re: MC68060 TT Behaviour

Post by exxos »

terriblefire wrote: Thu Dec 02, 2021 10:53 am Its a clock enable line. It means things have double the setup time. Every other clock is ignored externally but internally the CPU can chug away on things. I'm not seeing why this doesnt make sense?
Because it doesn't state disabling the clock, it says what clock edges it responds to, that by definition isn't a clock enable, it's more pulse skipping. If the clock was disabled, nothing would work, in which case 1/4 bus speed would be impossible. Plus it's talking about 3 speeds, so then sounds like the pin is multifunctional. Hence why I state it doesn't make sense.
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Re: MC68060 TT Behaviour

Post by terriblefire »

exxos wrote: Thu Dec 02, 2021 10:58 am
terriblefire wrote: Thu Dec 02, 2021 10:53 am Its a clock enable line. It means things have double the setup time. Every other clock is ignored externally but internally the CPU can chug away on things. I'm not seeing why this doesnt make sense?
Because it doesn't state disabling the clock, it says what clock edges it responds to, that by definition isn't a clock enable, it's more pulse skipping. If the clock was disabled, nothing would work, in which case 1/4 bus speed would be impossible. Plus it's talking about 3 speeds, so then sounds like the pin is multifunctional. Hence why I state it doesn't make sense.
This is the very definition of a Clock Enable. Its flip flop design 101.

From https://www.xilinx.com/html_docs/xilinx ... 93914.html
The purpose of the clock enable pin is to allow the flip-flop to hold a specific value for more than one clock pulse. New data inputs are only latched and passed to the data output port when both clock and clock enable are equal to one.
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Re: MC68060 TT Behaviour

Post by exxos »

What the data sheet says to me, is you sync and hold the rising edge with EN and wait 2 clock cycles then flip EN again. That would give the 1/4 speed it talks about. If you're doing that then it should be right.
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Re: MC68060 TT Behaviour

Post by terriblefire »

exxos wrote: Thu Dec 02, 2021 11:10 am What the data sheet says to me, is you sync and hold the rising edge with EN and wait 2 clock cycles then flip EN again. That would give the 1/4 speed it talks about. If you're doing that then it should be right.
Yes this is what i'm doing and that is the result i get.

Screenshot 2021-12-02 at 11.17.06.png
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I've tried it with the posedge and negedge just to be sure. Same result.

The issue is the TT signal is a full B Cycle (2 CPU clock cycles late). So we're already doing the wrong bus cycle by the time its right.
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Re: MC68060 TT Behaviour

Post by exxos »

I guess you could try a actual clock switch on the master clock ? See if the same oddness happens.

Also it doesn't quote how fast you can do the switching either. Could you try just doing a single one shot switch to see if it still screws up ?
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