BLITTER RE-CREATION THOUGHTS

Progress on our FPGA cores.
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Icky
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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky » Mon Oct 11, 2021 8:41 am

@Cyprian as @exxos mentions things are getting in the way a bit at the moment. Once I am set up after my move goes through I can hopefully swing back to this soon.

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Re: BLITTER RE-CREATION THOUGHTS

Post by rubber_jonnie » Mon Oct 11, 2021 9:14 am

@Icky The whole chip recreation thing is really amazing to me, and I was wondering if you have any good links that give an overview of the process i.e. How do you determine how the original Blitter operates and translate that into Verilog or VHDL?

You really sparked an interest in me when we spoke at the Centre for Computing History festival on Saturday. I may never be able to do it myself, but I'd love to know how it's done.
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Mon Oct 11, 2021 2:20 pm

@rubber_jonnie We are using the Suska core for a "quick" setup. @Icky has been working trying to get it cycle accurate for some time. We have tried all the other cores and the Suska one gives the best results out of the box.

If you look right back to the beginning of this thread we have the blitter schematic. We started converting this gate by gate to a FPGA schematic. But this was taking a incredibly long amount of time which is why we thought we would try working with the suka core instead. But there is some odd timing differences which I have not yet been able to solve hence it being 98% speeds not 100%.

Overall we do not know how the original blitter operates we can only basically guess, and with the program @Cyprian wrote we can analyse the timings to see if it matches the original or not. It is very close at the moment, but we do not know why still 2% slower than it should be. Unfortunately we could only guess and the whole thing by trial and error, basically stabbing in the dark what the fault is. As you can imagine this is a incredibly inefficient way of doing things, but there is really not much choice. Again this is why this project is taking such a long time and indeed why the MMU & GLUE cores are taking time to develop as well.

But as you can imagine by the length of this thread, is not easy, and we are both beginners at VHDL coding which is also holding things up somewhat.We try to get the MiST guys to help but I think they are just not interested in remake projects. Unfortunately the cores which they claim are cycle accurate, are far from it. Last time I checked they was running closure and deemed it as done and dusted. Unfortunately doing a lot of wrong things within the chipset is actually turning into a "fix". So when we run things one core at a time, it is completely messed up and basically unusable. It is why we are going with the Suska as it was originally developed as a stand-alone chipset.

We have been toying with managing the MMU,GLUE,BLITTER all into one FPGA for some time now, but again it is another project and a lot of work which we do not have time to do currently. We was thinking just forgetting the cycle accuracy for another time and just getting the cores working to the point where we can replace the custom ST chipsets and get them running at higher speeds. Because as soon as we break away from the 8MHz bus clock, system will not be cycle accurate any more anyway. We was thinking that the FPGA people really need to work on these problems not us. At the end of the day, if there is only myself and icky who is interested in cloning the original chipset 100% for a remake board, is it really worth spending basically years trying to do such work anyway.
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viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
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Re: BLITTER RE-CREATION THOUGHTS

Post by Badwolf » Mon Oct 11, 2021 2:36 pm

Great project this, which I've not been following.
exxos wrote:
Mon Oct 11, 2021 2:20 pm
We was thinking just forgetting the cycle accuracy for another time and just getting the cores working to the point where we can replace the custom ST chipsets and get them running at higher speeds.
This sounds like the way to go: get it good enough for 80% of the job and fix bugs as and when you can, or let users submit fixes down the line.
exxos wrote:
Mon Oct 11, 2021 2:20 pm
We have been toying with managing the MMU,GLUE,BLITTER all into one FPGA for some time now, but again it is another project and a lot of work which we do not have time to do currently.
CombelST, eh? If the board's routed for it, why not?

I suppose the big drawback would be limiting scope for replacements for existing STs, but if the FPGA does all three, I suppose you could have an adapter board that just taps off the bit that's required? The MMU adapter board, the GLUE adapter board, one for blitter. With the FPGA and HDL common to all three.

Fingers crossed you get there eventually. :-)

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Mon Oct 11, 2021 2:42 pm

Badwolf wrote:
Mon Oct 11, 2021 2:36 pm
CombelST, eh? If the board's routed for it, why not?

I suppose the big drawback would be limiting scope for replacements for existing STs, but if the FPGA does all three, I suppose you could have an adapter board that just taps off the bit that's required? The MMU adapter board, the GLUE adapter board, one for blitter. With the FPGA and HDL common to all three.
Because blitter is basically a add-on and impossible to find now, it is why we was trying to do a cycle accurate blitter for original machines.

In terms of a add-on board for the H5, I think @Icky Pretty much designed it a year ago. But we are trying to prove the chips will function as we think before embarking on another project.

In terms of original machines, it is not something we are really looking at. Having multiple small FPGA boards with all the IO buffers etc, I can pretty much take a guess they would end up at like £100 "a chip". I don't think it really makes sense to do that. The only people who would really want to repair the original hardware would be the purists, and they would have to find original chips in that case.
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viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
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Re: BLITTER RE-CREATION THOUGHTS

Post by sporniket » Mon Oct 11, 2021 4:35 pm

exxos wrote:
Mon Oct 11, 2021 2:20 pm
We was thinking that the FPGA people really need to work on these problems not us. At the end of the day, if there is only myself and icky who is interested in cloning the original chipset 100% for a remake board, is it really worth spending basically years trying to do such work anyway.
Yes, I just started on HDL this year (VHDL for now), and just changing the mindset and understanding what did go wrong in a piece of code "that should work".

As for me, nowadays I imagine (I always imagine lots of thing :D ) that I would combine the STE MCU, Shifter + sound buffers, and DMA on one side, and the CPU (optionnally multicore) + memory buffer/cache/blitter, alt ram on the other side. Now if only I could get motivated enough to write a testbench for a simple ripple counter... (I have all the knowledge to do it and get it to work, just need motivation...).

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Mon Oct 11, 2021 4:43 pm

sporniket wrote:
Mon Oct 11, 2021 4:35 pm
Yes, I just started on HDL this year (VHDL for now), and just changing the mindset and understanding what did go wrong in a piece of code "that should work".

As for me, nowadays I imagine (I always imagine lots of thing :D ) that I would combine the STE MCU, Shifter + sound buffers, and DMA on one side, and the CPU (optionally multicore) + memory buffer/cache/blitter, alt ram on the other side. Now if only I could get motivated enough to write a testbench for a simple ripple counter... (I have all the knowledge to do it and get it to work, just need motivation...).
With suska being a STE chipset, the work is already done. I want to expand on the DMA's and circuitry to have its own memory and not tie up the system at all.. Of course time is always a problem.

You mention alt-ram / cache etc, alt-ram is basically obsolete when we get the new chipset working because we were just simply have 14MB ST-RAM. If we can access this ultimately with a 020 / 030 CPU, we have caches anyway (but I like 020 better) and run the whole bus at 50mhz.. A lot of these alt-ram bodges just won't be needed.
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viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
Just because a lot of people agree on something, doesn't make it a fact. ~exxos ~

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Re: BLITTER RE-CREATION THOUGHTS

Post by sporniket » Mon Oct 11, 2021 5:55 pm

exxos wrote:
Mon Oct 11, 2021 4:43 pm
sporniket wrote:
Mon Oct 11, 2021 4:35 pm
As for me, nowadays I imagine (I always imagine lots of thing :D ) that I would combine the STE MCU, Shifter + sound buffers, and DMA on one side, and the CPU (optionally multicore) + memory buffer/cache/blitter, alt ram on the other side. Now if only I could get motivated enough to write a testbench for a simple ripple counter... (I have all the knowledge to do it and get it to work, just need motivation...).
With suska being a STE chipset, the work is already done.
Yes that's the plan, and I'm still in the learning phase though.
exxos wrote:
Mon Oct 11, 2021 4:43 pm
You mention alt-ram / cache etc, alt-ram is basically obsolete when we get the new chipset working because we were just simply have 14MB ST-RAM. If we can access this ultimately with a 020 / 030 CPU, we have caches anyway (but I like 020 better) and run the whole bus at 50mhz.. A lot of these alt-ram bodges just won't be needed.
I see. I agree that it is simpler this way. In my model, the alt-ram would be the main ram, because exclusive to the CPU (no bus sharing) and using the full-width and full speed of the CPU bus. ST-Ram would be secondary because shared between all peripherals, and with a slower and narrower bus. Obviously I am not aiming at full compatibility. Anyway as long as I am doing nothing, it's just "what if" things.

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Re: BLITTER RE-CREATION THOUGHTS

Post by mmx01 » Thu Nov 04, 2021 9:23 am

98% or 99% is much better than no blitter so I will experiment with this project as well. Interestingly it fits my Cyclone IV which is not the smallest package but doable by hand while Mega has got some room under the hood.

For bidirectional bus'es 3xGTL2000 will do the job with 66 lines available. Cyclone outputs could directly drive 5V logic but since there are only 3 no real gain or savings.

sdc files for fpga blitter are missing and on some pictures it has got dedicated crystal, wondering if that is 62,5 or traditional 50MHz.

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Thu Nov 04, 2021 10:32 am

What code are you actually using as we never published ours ?
https://www.exxoshost.co.uk/atari/ All my hardware guides - mods - games - STOS
https://www.exxoshost.co.uk/atari/store2/ - All my hardware mods for sale - Please help support by making a purchase.
viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
Just because a lot of people agree on something, doesn't make it a fact. ~exxos ~

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