The ram we have requires 20ns between RAS and CAS (ACT and RD here). So its got to be at least 2 clocks at 100Mhz. And the CAS latency (the time between CAS and data arriving on the bus) is 2 ram clock cycles. We have burst but lets just look at random access for now.
I'm using wavedrom for the diagrams..
Code: Select all
{signal: [
{name: 'CPU', wave: '345.....63|',data: ['S0', 'S1', 'S2', 'S3', 'S0']},
{name: 'CLKRAM', wave: 'p..................'},
{name: 'CLKCPU', wave: '1010101010101010101'},
{name: 'AS30', wave: '10........1|'},
{name: 'DS30', wave: '10........1|'},
{},
{name: 'CMD', wave: '.x3xx45xxxxxxxxxxxx',data: ['ACT', 'RD','RDP']},
{name: 'D', wave: 'x.......3.x...', data: ['data']},
{},
{name: 'STERM', wave: '1.......0.1|'}
]}